The present invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory device (DRAM) having memory cells each composed of one transistor and one storage capacitor.
In accordance with increase in memory capacity of a DRAM, an area which is able to be allotted to each memory cell, i.e. a cell size, is required be made small. The capacitance value of the storage capacitor is lowered accordingly. The decrease in capacitance value of the storage capacitor means that the amount of charges stored in the capacitor is made small, so that the data stored in each memory cell is easily destroyed.
In order to enhance the storage capacitance with a small cell size, therefore, a new stacked-type memory cell was proposed in "International Electron Devices Meeting Technical Digest", 1988, pp. 596-599, as titled "A New Stacked DRAM Cell Characterized by a storage Capacitor on a Bit-lone Structure". Referring to FIG. 1, this proposed memory cell is characterized in that the storage electrode 100 of the capacitor is stacked over a bit line 103. A dielectric film 101 is formed on the storage electrode 100, and a cell plate electrode 102 is formed on the film 101. Since the storage electrode 100 is formed over the bit line 103, the surface area thereof is made enlarged, so that the relatively large storage capacitance is obtained. Incidentally, the reference numerals 104 and 105 denote a word line and a diffusion region such a source or a drain region, respectively.
In order to further enhance the storage capacitance, however, the storage electrode 100 has only to be made thick to thereby enlarge the side surface area thereof. As a result, the flatness of the device is deteriorated to make it difficult that wiring patterns for interconnecting respective circuit elements are made fine.